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Authors: S. Selvaraja, G. Winroth, S. Locotorondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, P. Absil
Title: 193nm immersion lithography for high performance silicon photonic circuits
Format: International Conference Proceedings
Publication date: 2/2014
Journal/Conference/Book: 27th Optical Microlithography Conference as part of the SPIE Advanced Lithography Symposium
Editor/Publisher: SPIE, 
Volume(Issue): 9052 p.90520F
Location: San Jose, CA, United States
DOI: 10.1117/12.2049004
Citations: 17 (Web of Knowledge / Dimensions.ai - last update: 15/9/2020)
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Abstract

Large-scale photonics integration has been proposed for many years to support the ever increasing requirements for long and short distance communications as well as package-to-package interconnects. Amongst the various technology options, silicon photonics has imposed itself as a promising candidate, relying on CMOS fabrication processes.. While silicon photonics can share the technology platform developed for advanced CMOS devices it has specific dimension control requirements. Though the device dimensions are in the order of the wavelength of light used, the tolerance allowed can be less than 1% for certain devices. Achieving this is a challenging task which requires advanced patterning techniques along with process control. Another challenge is identifying an overlapping process window for diverse pattern densities and orientations on a single layer.


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