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Parallel optical interconnect systems

Main Researcher: Roel Baets

As the performance of electronic systems increases, the data rate inside these systems is reaching the limits of the traditional electrical interconnects over copper cables and metal tracks on printed circuit boards. Optical interconnections are proposed as a solution to this interconnect bottleneck. In current systems, one-dimensional parallel optical interconnects are used for intra-systems interconnects, as electrical cables are no cost-effective way of providing the required bandwidth. A next step is the introduction of optical interconnects inside the system, this is over the backpanel, ultimately leading to optical chip-to-chip interconnects. This is a hot research topic, and more and more chip companies are looking at this (see, for example, this link).

The research at the Photonics group is targetting the overall system design, and the specific challenges related to the low-cost and high-performance packaging of hybrid opto-electronic systems, where the digital chip, the transceiver and the opto-electronic components are combined in one package. The next figure shows the roadmap for this kind of data access: multi-100-gigabit-per-second data access is feasible today. For next-gneration CMOS technologies, or using fine-pitch optical pathways, multi-terabit-per-second data access can be relaised.

The roadmap for on-chip optical data access.
The roadmap for on-chip optical data access.

Next to this, the Photonics group is also involved as lead participant of the IST-IO project. In this consortium (consisting of mainly European companies), a complete family for parallel optical interconnects inside electronic systems is developed.

The IO system demonstrator.
The IO system demonstrator.

We cooperate with the PARIS group of the ELIS department of our university of the modeling aspects of parallel optical interconnects systems, and with the TFCG-INTEC group on the fabrication of the IO system demonstrator.

Other people involved:

Related Research Projects

PhD thesises

Patents

Publications

        International Conferences

      1. M. De Wilde, O. Rits, R. Bockstaele, J. Van Campenhout, R. Baets, A circuit-level simulation approach to analyse system level behaviour of VCSEL-based optical interconnects, VCSELs and Optical Interconnects. Proceedings of SPIE. Vol. 4942. 2003. , p.247-257  (2003).
      2. M. De Wilde, O. Rits, R. Bockstaele, R. Baets, J. Van Campenhout, Design Methodology Development for VCSEL-based Guided-Wave Optical Interconnects, Proceedings of the 7th IEEE Workshop on Signal Propagation on Interconnects. IEEE. 2003. , p.137-138  (2003).
      3. R. Bockstaele, I. Popov, S. Eitel, M. Klemenc, R. Annen, J. Van Koetsem, G. Widawski, P. Straub, P. Le Moine, F. Marion, R. Baets, A low-cost parallel optical interconnect system: the IO link, IEEE/LEOS Benelux Chapter, (2003).
      4. M. De Wilde, O. Rits, Design methodology development for guided-wave optical interconnects, Design, Automation and Test in Europe. 2003, (2003).
      5. M. De Wilde, O. Rits, R. Bockstaele, J. Van Campenhout, R. Baets, A circuit-level simulation approach to analyse system level behaviour of VCSEL-based optical interconnects, SPIE, 4942, Belgium, (2002)  Download this Publication (312KB).
          National Conferences

        1. R. Bockstaele, Interconnect by Optics, Project overview & Work on Plastic Optical Fibre, POFAC Fachgruppentreffen (invited), Germany, (2004).
        2. R. Bockstaele, et al., A low-cost parallel optical interconnect system: the IO link, RMA workshop on POF, (2003).

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