3D Integration of Photonics & CMOS using Cu Through-Silicon-Via

Research Area: Photonics packaging , Photonics-electronics convergence, Silicon photonics for telecom, datacom and interconnect

Main Researcher: Adil Masood

To realize their potential, Nanophotonic circuits will ultimately need tight integration with electronics. The scale of Nanophotonics allows for thousands of components on a single photonic chip, many of which need to be tuned, driven or monitored. This requires electronics functions on a similar integration scale. Applications can be found in a variety of fields, ranging from telecommunication over sensing to biomedical application. This variety introduces a need for a flexible integration technology that can handle low-cost and high-volume demands, but also high-performance components.

The objective is to integrate photonics and electronics in a way that minimizes the limitations set to both the electronics and the photonic chips. For this, Stacked IC approach will be used, which involves bonding the photonics on the electronics, and using Through-Silicon-Via (TSVs) to connect both. Cu-nail TSVs can directly contact both layers, with via counts in the order of thousands or more.

3D Integration of Photonics & CMOS using Cu-Nails (TSVs)

This technological development will lead to new capabilities, which in turn can be leveraged to implement new functionality. This combines both technology in Ghent and IMEC (Leuven), and therefore there will be follow-up by people from all relevant groups.

Other people involved:

• Adil Masood

Related Research Projects

• IWT-SBO: GlucoSens (Enabling technologies for continuous glucose monitoring using implantable single-chip optical sensors)